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ADSP-SC596 데이터시트(PDF) 121 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 121 Page - Analog Devices

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Rev. PrD
|
Page 121 of 134
|
May 2022
ADSP-SC595/SC596/SC598
Preliminary Technical Data
Pulse Density Modulation (PDM) Timing
Table 84, Figure 63, and Figure 64 provide PDM and I2S/TDM interface timing.
Table 84. PDM Timing
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tLIS
FSYNC Setup Before BCLK
3
ns
tLIH
FSYNC Hold After BCLK
4
ns
tBIH
BCLK Pulse Width High
10
ns
tBIL
BCLK Pulse Width Low
10
ns
tSETUP
Data Setup Before PDM_CLK
12
ns
tHOLD
Data Hold After PDM_CLK
4
ns
Switching Characteristic
tSODM
SDATA Maximum Output Delay From BCLK Falling Edge
12
ns
Figure 63. Serial Port Timing
Figure 64. PDM Timing
BCLK
LRCLK
SDATA
TDM MODE
SDATA
I2S JUSTIFIED
MODE
tBIH
MSB
MSB
MSB – 1
tBIL
tLIS
tLIH
tSODM
tSODM
L
R
tHOLD
tSETUP
PDM_CLK
PDM_DAT
L
R



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