ADSP-SC596 datasheet(124/134 Pages) AD

124 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 124 of 134

May 2022

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 72

shows the measurement point for ac measurements (except out-

put enable/disable). The measurement point, VMEAS, is

VDD_EXT/2 for VDD_EXT (nominal) = 3.3 V.

Output Enable Time Measurement

Output pins are considered enabled when they make a transi-

tion from a high impedance state to the point when they start

driving.

The output enable time, tENA, is the interval from the point

when a reference signal reaches a high or low voltage level to the

point when the output starts driving, as shown on the right side

of Figure 73. If multiple pins are enabled, the measurement

value is that of the first pin to start driving.

Output Disable Time Measurement

Output pins are considered disabled when they stop driving,

enter a high impedance state, and start to decay from the output

high or low voltage. The output disable time, tDIS, is the interval

from when a reference signal reaches a high or low voltage level

to the point when the output stops driving, as shown on the left

side of Figure 73).

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 74). VLOAD is equal

to VDD_EXT/2. Figure 75 through Figure 78 show how output

rise time varies with capacitance. The delay and hold specifica-

tions given must be derated by a factor derived from these

figures. The graphs in Figure 75 through Figure 78 cannot be

linear outside the ranges shown.

Figure 71. Driver Type B and Driver Type C (DDR3L Drive Strength 100 Ω)

Figure 72. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

–14

–12

–10

–8

–6

–4

–2

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

SOURCE VOLTAGE (V)

VOL

VDD = 1.418V AT –40°C

VDD = 1.350V AT +25°C

VDD = 1.285V AT +125°C

INPUT

OUTPUT

VMEAS

Figure 73. Output Enable/Disable

Figure 74. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

ZO = 50

(impedance)

TD = 4.04

1.18 ns

2pF

TESTER PIN ELECTRONICS

0.5pF

400

4pF

NOTES:

THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

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