전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ADSP-SC596 데이터시트(PDF) 106 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 106 Page - Analog Devices

Back Button ADSP-SC596 Datasheet HTML 102Page - Analog Devices ADSP-SC596 Datasheet HTML 103Page - Analog Devices ADSP-SC596 Datasheet HTML 104Page - Analog Devices ADSP-SC596 Datasheet HTML 105Page - Analog Devices ADSP-SC596 Datasheet HTML 106Page - Analog Devices ADSP-SC596 Datasheet HTML 107Page - Analog Devices ADSP-SC596 Datasheet HTML 108Page - Analog Devices ADSP-SC596 Datasheet HTML 109Page - Analog Devices ADSP-SC596 Datasheet HTML 110Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 106 / 134 page
background image
Rev. PrD
|
Page 106 of 134
|
May 2022
ADSP-SC595/SC596/SC598
Preliminary Technical Data
Table 71. Enhanced Parallel Peripheral Interface (EPPI)—External Clock
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
EPPI_CLK Width1
0.5 × tPCLKEXT – 0.5
ns
tPCLK
EPPI_CLK Period1
tPCLKEXT – 1
ns
tSFSPE
External FS Setup Before EPPI_CLK
2
ns
tHFSPE
External FS Hold After EPPI_CLK
3.7
ns
tSDRPE
Receive Data Setup Before EPPI_CLK
2
ns
tHDRPE
Receive Data Hold After EPPI_CLK
3.7
ns
Switching Characteristics
tDFSPE
Internal FS Delay After EPPI_CLK
15.3
ns
tHOFSPE
Internal FS Hold After EPPI_CLK
2.4
ns
tDDTPE
Transmit Data Delay After EPPI_CLK
15.3
ns
tHDTPE
Transmit Data Hold After EPPI_CLK
2.4
ns
1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 22.
Figure 45. EPPI External Clock GP Receive Mode with Internal Frame Sync Timing
Figure 46. EPPI External Clock GP Transmit Mode with Internal Frame Sync Timing
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
tDFSPE
tPCLK
tPCLKW
EPPI_D00-23
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 10
POLC[1:0] = 01
tHOFSPE
FRAME SYNC
DRIVEN
DATA
DRIVEN
tDFSPE
tDDTPE
tHDTPE
tPCLK
tPCLKW
DATA
DRIVEN
EPPI_D00-23
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com