ADSP-SC596 datasheet(108/134 Pages) AD

108 / 134 page

Rev. PrD

Page 108 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Extended Mobile Storage Interface (eMSI) Controller Timing—eMMC SDR Mode

Table Table 72 and Figure 49 show I/O timing related to the eMSI.

Table 72. eMSI Controller Timing—eMMC SDR Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tWL

CLK Low Time

0.45 × tP

0.55 × tP

tWH

CLK High Time

0.45 × tP

0.55 × tP

Clock Frequency Data Transfer Mode1

1 tP = 1/fP

MHz

tPP

Period

tP – 0.8

tISU

Input Data Setup Time

5.8

tIH

Input Data Hold Time

2.5

tISU

Input Command Setup Time

5.8

tIH

Input Command Hold Time

2.5

Switching Characteristics

tODLY

Output Data Delay

16.5

tOH

Output Data Delay

3.5

tODLY

Output Command Delay

16.5

tOH

Output Command Delay

3.5

Figure 49. eMSI Controller Timing with eMMC SDR Mode

tIH

DATA

tWH

tWL

tPP

CLK

INPUT

OUTPUT

DATA

tISU

tOH

tODLY

INVALID

DATA

INVALID

DATA

ADSP-SC596 데이터시트(PDF) 108 Page - Analog Devices

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