ADSP-SC596 datasheet(111/134 Pages) AD

111 / 134 page

Rev. PrD

Page 111 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Sony/Philips Digital Interface (S/PDIF) Transmitter

Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits.

The following sections provide timing for the transmitter.

S/PDIF Transmitter Serial Input Waveforms

Table 75 and Figure 52 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on

the rising edge of the serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a

frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next

frame sync transition.

Table 75. S/PDIF Transmitter Right Justified Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Conditions

Nominal

Unit

Timing Requirement

tRJD

Frame Sync to MSB Delay in Right Justified Mode

16-bit word mode

SCLK0

18-bit word mode

SCLK0

20-bit word mode

SCLK0

24-bit word mode

SCLK0

Figure 52. Right Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1

MSB–2

LSB+2

LSB+1

DAI_P20–1

SCLK0

DAI_P20–1

SDATA

tRJD

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