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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADSP-SC596 데이터시트(PDF) 115 Page - Analog Devices |
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ADSP-SC596 데이터시트(HTML) 115 Page - Analog Devices |
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115 / 134 page  Rev. PrD | Page 115 of 134 | May 2022 ADSP-SC595/SC596/SC598 Preliminary Technical Data MediaLB (MLB) All the numbers shown in Table 81 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unless otherwise specified. Refer to the Media Local Bus Specification Version 4.2 for more details. Table 81. 3-Pin MLB Interface Specifications All specifications are based on simulation data and are subject to change without notice. Parameter Min Typ Max Unit tMLBCLK MLB Clock Period 1024 FS 512 FS 256 FS 20.3 40 81 ns ns ns tMCKL MLBCLK Low Time 1024 FS 512 FS 256 FS 6.1 14 30 ns ns ns tMCKH MLBCLK High Time 1024 FS 512 FS 256 FS 9.3 14 30 ns ns ns tMCKR MLBCLK Rise Time (VIL to VIH) 1024 FS 512 FS/256 FS 1 3 ns ns tMCKF MLBCLK Fall Time (VIH to VIL) 1024 FS 512 FS/256 FS 1 3 ns ns tMPWV 1 1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak. MLBCLK Pulse Width Variation 1024 FS 512 FS/256 0.7 2.0 nspp nspp tDSMCF DAT/SIG Input Setup Time 1 ns tDHMCF DAT/SIG Input Hold Time 2 ns tMCFDZ DAT/SIG Output Time to Three-State 0 15 ns tMCDRV DAT/SIG Output Data Delay From MLBCLK Rising Edge 8 ns tMDZH 2 2 Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Bus Hold Time 1024 FS 512 FS/256 2 4 ns ns CMLB DAT/SIG Pin Load 1024 FS 512 FS/256 40 60 pf pf |
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