ADSP-SC596 datasheet(113/134 Pages) AD

113 / 134 page

Rev. PrD

Page 113 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given in Table 78. Input signals are routed to the DAI0_PINx pins using the SRU.

Therefore, the timing specifications provided below are valid at the DAI0_PINx pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the

internal biphase clock.

Table 78. S/PDIF Transmitter Input Data Timing

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSISFS

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the

PCG can be either CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge

3.4

tSIHFS

Frame Sync Hold After Serial Clock Rising Edge

tSISD

Data Setup Before Serial Clock Rising Edge

tSIHD

Data Hold After Serial Clock Rising Edge

tSITXCLKW

Transmit Clock Width

tSITXCLK

Transmit Clock Period

tSISCLKW

Clock Width

tSISCLK

Clock Period

Figure 55. S/PDIF Transmitter Input Timing

Table 79. Oversampling Clock (TxCLK) Switching Characteristics

All specifications are based on simulation data and are subject to change without notice.

Parameter

Max

Unit

Switching Characteristics

fTXCLK_384

Frequency for TxCLK = 384 × Frame Sync

Oversampling ratio × frame sync ≤ 1/tSITXCLK

MHz

fTXCLK_256

Frequency for TxCLK = 256 × Frame Sync

49.2

MHz

fFS

Frame Rate (FS)

192

kHz

SAMPLE EDGE

DAI0_PIN20–1

(TxCLK)

DAI0_PIN20–1

(SCLK0)

DAI0_PIN20–1

(FS)

DAI0_PIN20–1

(SDATA)

tSITXCLKW

tSITXCLK

tSISCLKW

tSISCLK

tSISFS

tSIHFS

tSISD

tSIHD

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